1. Field of the Invention
This invention relates to a clock drive circuit which feeds clock signals to flipflops constituting a logic system and, in particular, to a clock drive circuit having a small clock skew which is suitable for increasing the working speed of the logic system.
2. Description of the Related Art
In order to form a high speed logic system, it is necessary to decrease clock skew by reducing delay time fluctuations in a plurality of clock drive circuits which feed clock signals to a number of flipflops within a logic system. As a method for reducing the clock skew, there is known a clock feeding method, as disclosed, e.g. in "1987 ISSCC Digest of technical papers", pp. 86-87, by which in order to feed clock signals to a number of flipflops within a logic system, differences in delay time associated with the clock input terminal of different flipflops are decreased so as to reduce the clock skew by distributing clock signals through a multi-stage buffer circuit and by unifying the fan-out and the wiring length of each of the stages.
In the clock drive circuit of a final stage in a clock feeding system which generates clock input signals for the flipflops, it is necessary to AND various sorts of condition signals for setting data in these flipflops and to use various sorts of logic circuits having different numbers of inputs. According to the prior art techniques described above, apart from the delay time in the clock drive circuit of the last stage, it is possible to reduce fluctuations in the other delay times in the clock feeding system and to achieve delay time fluctuations within the range of fluctuations being determined at the fabrication of semiconductor devices. However, when it is desired to further increase the working speed of the logic system, fluctuations in the signal delay time of the clock drive circuit in the final stage of the clock feeding system which have a number of inputs corresponding to logic functions give rise to other problems.